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Freescale Semiconductor /MKL28T7_CORE1 /FLEXIO0 /FLEXIO0_TIMCTL7

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Interpret as FLEXIO0_TIMCTL7

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (00)TIMOD 0 (0)PINPOL 0PINSEL0 (00)PINCFG 0 (0)TRGSRC 0 (0)TRGPOL 0TRGSEL

PINCFG=00, TRGSRC=0, TRGPOL=0, TIMOD=00, PINPOL=0

Description

Timer Control N Register

Fields

TIMOD

Timer Mode

0 (00): Timer Disabled.

1 (01): Dual 8-bit counters baud/bit mode.

2 (10): Dual 8-bit counters PWM mode.

3 (11): Single 16-bit counter mode.
PINPOL

Timer Pin Polarity

0 (0): Pin is active high

1 (1): Pin is active low
PINSEL

Timer Pin Select
PINCFG

Timer Pin Configuration

0 (00): Timer pin output disabled

1 (01): Timer pin open drain or bidirectional output enable

2 (10): Timer pin bidirectional output data

3 (11): Timer pin output
TRGSRC

Trigger Source

0 (0): External trigger selected

1 (1): Internal trigger selected
TRGPOL

Trigger Polarity

0 (0): Trigger active high

1 (1): Trigger active low
TRGSEL

Trigger Select

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data